IP cores for the embedded GNSS-SDR

An instance of GNSS-SDR processing signals in real-time demands a multi-core CPU and a high-bandwidth SDR front-end attached as a peripheral via USB or Ethernet. This usually involves a Commercial Off-the-Shelf (COTS) computer, with electric consumption in the range of 30-60 Watts (e.g., an Intel’s NUC running GNSS-SDR single frequency, 16 channels at 8 MSps). Embedded micro-computers platforms, such as the popular Raspberry PI4 that consumes around 9 W under full load, can be used to run GNSS-SDR in real-time but the available computing power severely limits the number of channels (that is, satellites) and the sampling frequency, to the point that makes the software almost unusable in real-time mode.

A suitable implementation alternative for embedding GNSS-SDR in a lightweight and low power device is the use of a System-on-Chip (SoC) module, like the ones of the AMD/Xilinx Zynq SoC family, splitting the GNSS signal processing chain in two different sections, which is usually known as FPGA off-loading:

  • High speed, low complexity but highly demanding operations, such as the FFT and correlations, are implemented in the SoC FPGA fabric.
  • Low speed but high complexity operations, like the tracking control loops, the decoding of the navigation messages, the formation of observables, and the PVT solver are implemented in the SoC ARM processor(s).

The embedded receiver keeps almost all the flexibility of the pure SDR version of GNSS-SDR such as the inspection of any internal signal and the customization of acquisition or tracking loops parameters or even the complete customization of the implemented algorithms, but the whole process is accelerated by our FPGA IP cores.

Next pictures show a complete GNSS SDR embedded receiver FPGA instantiation using the G-ACQ-ST and G-TRK-ST IP cores:

Rx1 Rx2 GNSS receiver FPGA instantiation. Don’t be overwhelmed, you will get detailed instructions and a working example about how to do that.

Embedding GNSS-SDR in a SoM device such as the ADRV936x System on Module reduces the power consumption to 5-6 Watts and supports real-time, dual band multi-constellation GNSS processing with:

  • 6 GPS L1 CA channels at 12.5 MSps,
  • 6 Galileo E1 channels at 12.5 MSps,
  • 6 GPS L5 channels at 12.5 MSps, and
  • 6 Galileo E5a channels at 12.5 MSps.

Other custom implementations or configurations can be instantiated by the user. The software executed in the SoC processing system (PS) is completely open source and already available in the GNSS-SDR upstream repository.

In order to enable the execution of the FPGA-accelerated, embedded GNSS-SDR in the AMD/Xilinx Zynq, Zynq Ultrascale, and Zynq Ultrascale+ families, CTTC have developed a set of commercial IP cores to bootstrap the customer to create GNSS-SDR powered embedded products.

The GNSS-SDR FPGA IP portfolio currently offers two main IP cores:

  • G-ACQ-ST implements a parallel-code search / serial frequency search GNSS acquisition accelerator algorithm with standard sensitivity (35 dB-Hz).
  • G-TRK-ST implements a multi-correlator and carrier wipe-off accelerator algorithm for tracking any current GNSS signals.

More information about each IP core is provided below.

G-ACQ-ST: GNSS-SDR standard acquisition IP core

G-ACQ-ST The G-ACQ-ST IP Core interface.

The G-ACQ-ST FPGA IP core implements a Parallel Code Phase Search (PCPS) algorithm to detect the presence/absence of signals coming from a given GNSS satellite. In the case of a positive detection, it provides estimations of the code phase and the Doppler shift of the detected signal.

The PCPS algorithm is implemented using an FFT and zero-padding. The FPGA runs the complete acquisition algorithm, including the Doppler search, without any CPU intervention.

G-TRK-ST: GNSS-SDR tracking IP core

G-TRK-ST The G-TRK-ST IP Core interface.

The G-TRK-ST FPGA IP core implements Doppler wipe-off, multi-correlation, and resampling of the local replica of the PRN codes and secondary codes in real-time.

This IP core correlates the incoming signal with a local replica of the pilot and data PRN codes and secondary codes in order to derive estimates of the Doppler frequency and code phase of the received signals, and to keep the ‘Prompt’ correlator aligned with the incoming signal. The core implements a configurable number of correlators that can be configured as follows:

  • E, P, L (Early, Prompt, and Late) correlators for the signal’s Data component.
  • E, P, L correlators for the signal’s Pilot component, and an extra P correlator for the Data component.
  • VE, E, P, L, VL (Very Early, Early, Prompt, Late, and Very Late) correlators for the Pilot component, and an extra P correlator for the Data component.

The local replica of the PRN codes and secondary codes are automatically resampled to the sampling frequency of the received signal. The coherent integration time is configurable.